The disclosed invention generally relates to CMOS integrated circuit processing techniques for forming source and drain regions, and is more particularly directed to a CMOS process for forming source and drain regions for sub-half-micron devices which can operate at voltages higher than 5 volts.
Advances in CMOS integrated circuit processing have made sub-half-micron active devices possible. As devices are made smaller, the doping of the substrate in which the devices are formed is increased to prevent punch-through. The increased substrate doping produces a steep doping concentration gradient across the source/substrate and drain/substrate metallurgical junctions, which increases the field across the junctions. In N-channel devices, the increased electric field increases impact ionization which generates electron-hole pairs. The generated holes present a problem of "snapback" (parasitic n-p-n bipolar transistor action), while the generated electrons present a problem of gate oxide charging.
Snapback occurs when the lateral parasitic n-p-n bipolar transistor (source-substrate-drain) is turned on by the large impact ionization current from the drain before the substrate-drain diode breaks down. The minimum drain voltage at which snapback occurs, called the snapback voltage, decreases as the drain/substrate electric field increases. The snapback problem is worse where the starting substrate material is N type, since a high P-well sheet resistance results in a high effective base resistivity of the lateral parasitic bipolar transistor.
As the field along the channel becomes high, some electrons generated by impact ionization can acquire sufficient energy (hot electrons) to be injected into the gate oxide. Gate oxide charging, which continues to increase with time during device operation, is detrimental to the long term operation of a device.
An analysis of snapback and other short channel effects are discussed in Physics of Semiconductor Devices, Second Edition, Sze, pages 480-486 (1981).
A further consideration with smaller devices is the increased susceptibility to latch-up conditions.
Another consideration with CMOS processing of sub-half-micron devices is increased threshold voltage resulting from oxidizing the polysilicon gates after they have been patterned. The oxidation encroaches beneath the polysilicon gates adjacent the source and drain regions which, by virtue of the small size of the device, are controlled to underlap the polysilicon gates by a very small amount. If the encroaching oxide extends over sharply defined source and drain junctions, the increased oxide thickness will produce regions in the channels with substantially higher threshold voltages, and also causes problems in controlling threshold voltage variation.